Semiconductor chip designers commonly write their circuit design definitions in a high-level design language, such as a register-transfer level (RTL) definition written in a standardized hardware-description language (HDL), for example Verilog or VHDL. Designers then use simulation tools to debug the design and verify that it will function as required by the circuit specification. A variety of simulation and verification tools that can be used for these purposes are known in the art, such as the Incisive® Enterprise Simulator offered by Cadence Design Systems, Inc. (San Jose, Calif.).
Once the RTL circuit definition has been completed and verified, it is synthesized automatically into a gate-level netlist. Synthesis tools for this purpose include, for example, the Genus™ Synthesis Solution offered by Cadence Design Systems, Inc. Other companies, such as Synopsys, Inc. (Mountain View, Calif.), offer comparable simulation, verification, and synthesis tools. After synthesis of the netlist, the design process continues, using the netlist, to physical design and layout.